Technical expert in Power analysis & optimization, Low Power Design – synthesis, place & route (P&R), timing convergence. I am adept in using Synopsys BE design tools including design compiler, ICC2 P&R, ICC P&R, Primetime, PTPX, and coding UPF, TCL, Python.

I have advanced knowledge of SOC Fabric Design, Design for test (DFT), ICC2 Design planning, Layout verification, DRC clean-up, LEC Formal Verification, VCS, Verdi, Logic/RTL Design, Test planning, pre-Si verification, System Verilog, Verilog, OVM.

I have experience leading teams of experienced engineers as well as new-grads on multiple projects.

I have pre-Si design experience, from design exploration phase to tape-out, in BE & FE design roles in various process nodes.

I am a champion for inclusion at work-place and enjoy mentoring and advocating for Women in STEM careers. I served as Co-chair, 2021 and Treasurer, 2020 for Santa Clara Valley (SCV) IEEE Women in Engineering (WIE). I also served as Treasurer for IEEE SCV Young Professionals and was part of SCV section election committee in 2021. I have been Co-chair for Women at Intel (WIN) Santa Clara chapter for 2020-2021. I volunteered with several non-profits focused on Women in Engineering & Technology and STEM education like FIRST, MentorNet, MakerFaire, Women in BigData.