Women in Big Data Global 
Donate
×
October 26, 2026
Women in Big Data, Women in AI Hardware, Semiconductor & Data Science, and Siemens EDA bring industry leaders together to explore power-efficient AI hardware design.
On September 17, 2026, Women in Big Data (WiBD), together with our sister organization Women in AI Hardware, Semiconductor & Data Science, and in collaboration with Siemens EDA, hosted an insightful panel at AI Infra Summit 2026 at the Santa Clara Convention Center.
The session, “Power Analysis, Power-Aware Design & Verification Challenges & Innovations for AI Hardware,” brought together semiconductor and electronic design automation (EDA) leaders to explore one of the most pressing challenges facing AI infrastructure: how to deliver increasingly powerful AI systems while managing energy consumption, thermal constraints, and design complexity.
As AI workloads push the limits of computing infrastructure, power efficiency has become a critical consideration throughout the semiconductor design lifecycle—from architecture and specification to verification, physical implementation, and testing.
The discussion explored the implications for AI chips, accelerators, GPUs, data centers, cloud infrastructure, and inference hardware, highlighting the industry’s shift from performance-centric design toward power-aware methodologies.
The panel featured three accomplished semiconductor industry leaders:
Priya Joshi
Director, Program Management, d-Matrix
Priya is a semiconductor industry veteran with extensive experience across CPU and ASIC products, spanning IoT, mobile, data centers, EDA, and AI computing.
Jagjot Kaur
Technology Enablement Director, Siemens EDA
Jagjot brings 20 years of experience in semiconductor design and EDA, with deep expertise in design for testability (DFT) and previous roles at Freescale, Texas Instruments, Qualcomm, Intel, Cadence, and Siemens EDA.
Monika Venkateshmurthy
Technical Program Manager, MatX
Monika is a semiconductor industry veteran and former Intel Principal Engineer with 28 years of experience leading complex chip-design programs and driving engineering and workflow transformation.
The discussion was moderated by Rupa Gangatirkar, AI/ML Solutions Architect at Siemens EDA, co-founder of Women in AI Hardware, Semiconductor & Data Science, and Director of WiBD’s Global Hackathon Program.
The discussion opened with a striking comparison: the human brain operates on approximately 20 watts, while modern AI infrastructure requires enormous amounts of electricity, with advanced accelerators consuming more than 1,000 watts and large data centers operating at megawatt scale.
This contrast illustrates the growing importance of energy efficiency as AI systems become more powerful and complex.
The panelists emphasized that power can no longer be treated as a secondary consideration addressed late in the design process. Instead, it must be integrated into architectural decisions, IP selection, design verification, physical implementation, and testing.
The conversation also highlighted the growing importance of tokens per watt as a measure of AI hardware efficiency—shifting attention from raw computing performance toward the amount of useful AI processing delivered for a given amount of energy.
Power-aware design must begin at the earliest stages of chip development.
The panelists emphasized the importance of understanding power requirements when defining the architecture, selecting intellectual property (IP), and designing custom logic.
Accurate power intent specifications, including Unified Power Format (UPF) power-state tables, help teams establish appropriate operating modes and avoid costly changes later in the development cycle.
As one panelist explained:
“The thought process behind designing your chip starts at the reticle. Right at the architecture step, when you’re figuring out which IPs to procure and which custom designs to develop, you need a good understanding of the power impact associated with each of them.”
The key message: Power efficiency must be designed into AI hardware from the beginning, not optimized as an afterthought.
Priya Joshi highlighted the challenges of projecting power consumption for AI chips when workloads, architectures, and numerical formats are changing rapidly.
Unlike traditional CPU designs, which benefit from established benchmarks and workload traces, AI accelerators often lack standardized benchmarks that accurately represent real-world operating conditions.
Design teams must therefore develop power projections based on assumptions about workloads, compute engines, pipelines, and data movement, refining those estimates as implementation progresses.
Tools such as PrimePower and PowerArtist provide valuable early estimates, but correlation between register-transfer level (RTL) analysis and later physical-design results remains challenging.
Clock-tree synthesis, placement, routing, and buffering can introduce significant differences between early projections and final power consumption.
The panel emphasized the importance of iterative estimation, realistic guard bands, and continuous validation throughout the design lifecycle.
Monika Venkateshmurthy explored how the massive scale and architecture of modern AI accelerators introduce new challenges for clock distribution and power management.
Large tensor-processing arrays contain numerous replicated computing units spread across substantial physical areas. Traditional fine-grained clock-gating techniques may not deliver the same benefits in these environments.
Design teams must consider clock-network architecture, gating granularity, skew, latency, voltage drops, and power delivery together.
The discussion also highlighted the importance of optimizing numerical formats, including INT4 and INT8, to reduce data movement and switching activity.
Monika captured the broader implications of power consumption with a memorable observation:
“Every toggle that you do has two costs associated: one is the electricity to toggle it, and the second is how you are going to cool it.”
This reinforces an important principle: Reducing switching activity can lower both electricity consumption and cooling requirements, improving the overall cost and scalability of AI infrastructure.
Jagjot Kaur discussed the growing complexity of design for testability (DFT) as semiconductor designs become larger and more power-intensive.
DFT operations can activate millions of flip-flops simultaneously, generating significantly more switching activity than typical functional workloads.
In some cases, test activity can draw two to five times more power than normal operating modes, creating substantial thermal risks.
Jagjot emphasized the need for a shift-left approach, incorporating power estimation, test-point planning, and thermal considerations earlier in the design process.
Thermal-aware test scheduling can help prevent excessive power consumption while balancing test coverage, test time, and test-data volume.
As AI chips grow increasingly complex, power-aware DFT is becoming essential to protecting silicon reliability and maintaining manufacturing efficiency.
Chiplet architectures offer new opportunities to scale AI computing, but they also introduce significant power delivery, thermal, and integration challenges.
The panel explored how moving from monolithic chips to multi-die architectures transforms traditional design concerns into three-dimensional integration problems.
Power integrity, signal integrity, timing, and thermal management must now be evaluated across dies, interposers, and packages.
Additional challenges include differing manufacturing schedules, package cooling requirements, microbump current density, and the complexity of three-dimensional timing and power signoff.
The discussion reinforced the need for closer collaboration across semiconductor architecture, physical design, packaging, verification, and manufacturing teams.
Successful chiplet integration requires treating power and thermal management as system-level design responsibilities rather than isolated chip-level tasks.
A recurring theme throughout the panel was the need to move beyond traditional measures of computing performance.
As AI systems scale, the challenge is no longer simply to add more processing capability. It is to deliver greater intelligence and throughput within increasingly demanding power, thermal, and cost constraints.
This requires collaboration across hardware architecture, software development, physical implementation, verification, and testing.
The panelists emphasized that power optimization decisions made in one area can have significant consequences throughout the broader AI ecosystem.
The emerging focus on tokens per watt reflects this shift toward evaluating AI hardware based on energy-efficient performance rather than raw computing capacity alone.
Ultimately, the next generation of AI infrastructure will depend on how effectively organizations balance performance, energy efficiency, reliability, and cost.
The panel concluded with an interactive question-and-answer session, giving attendees an opportunity to raise practical questions and share challenges from their own design and verification experiences.
The exchange reinforced the importance of bringing together industry experts to address increasingly complex engineering problems.
It also highlighted the valuable contributions of women leaders working at the forefront of semiconductor innovation, AI hardware development, and electronic design automation.
Women in Big Data extends its sincere appreciation to Priya Joshi, Jagjot Kaur, and Monika Venkateshmurthy for sharing their expertise and practical insights.
Special thanks to Rupa Gangatirkar for moderating the discussion and helping bring this important topic to the AI Infra Summit stage.
We also thank Siemens EDA for its collaboration and support in making this panel possible.
Our appreciation goes to WiBD Co-founder and Executive Board Member Shala Arshi for her continued guidance and support in bringing WiBD’s first panel to AI Infra Summit.
We are equally grateful to the AI Infra Summit Programs and Portfolio Committee members Priya Khosla, Ruby Goodall, and Eleanor Wilson for providing the opportunity, coordination, and logistical support that helped make this session a success.
As artificial intelligence continues to transform industries, the demand for more capable and energy-efficient computing infrastructure will only accelerate.
The insights shared at AI Infra Summit 2026 underscored a critical shift: The future of AI hardware will be defined not only by how much computing power we can deliver, but by how intelligently and efficiently we use energy.
Through collaborations like this, Women in Big Data and Women in AI Hardware, Semiconductor & Data Science continue to create opportunities for women leaders to share expertise, advance technical discussions, and contribute to the innovations shaping the future of AI infrastructure.
01/17/24
Feel like socializing?
Interested in serving on a Women in Big Data leadership committee?
Click here to let us know.